1. Field of the Invention
This invention relates to a method of fabricating a semiconductor device, more particularly to a method of fabricating a field effect transistor having a gate-drain overlap structure.
2. Description of the Prior Art
The size of semiconductor devices, for example, MOS-type field effect transistors (MOSFETs) constituting integrated circuits (ICs) is becoming smaller and smaller. For miniaturizing the dimension of MOSFETs and other devices, many kinds of device structures and methods of fabricating these devices have been proposed. The reduction of device dimensions has allowed improvements of device performance as well as an increase in the number of devices. However, the supply voltages have not been scaled down with the device dimension due to the system constrains that require an IC to interface with many ICs that need to run at the same voltages. Therefore, miniaturizing the dimension of the MOSFETs increased the internal electric field in the MOSFETs, and this result in reliability problems due to effects such as a short channel effect and a hot carrier effect.
A GOLD (a gate-drain overlapped LDD) structure has been proposed to achieve high reliability and high performance in deep submicron MOSFET (Izawa et. al., International Electron Device Meeting Technical Digest of Papers, pp. 38-41, 1987). According to the GOLD structure, the internal electric field at the edge part of the drain can be reduced.
Referring to FIGS. 12A to 12D, we will describe the prior art method of fabricating the GOLD MOSFET. As shown in FIG. 12A, a gate oxide film 112, a thin lower polycrystalline silicon film (poly-Si film) 120, a thick upper poly-Si film 150 and a silicon oxide layer 160 are sequentially formed on a p-type single crystalline silicon semiconductor layer 100. In these steps, before depositing the thick upper poly-Si film 150 on the thin lower poly-Si film 120, a thin native oxide film which is formed on the surface of the thin lower poly-Si film 120 is not removed. This leads to the presence of the native oxide film (not shown) having a thickness of 0.5 to 1 nm at the interface between the poly-Si film 150 and the poly-Si film 120.
A resist pattern 170 is then formed by conventional photolithography steps. As shown in FIG. 12B, after forming an oxide film pattern 160A using the resist pattern 170 as an etching mask, by further using this oxide film pattern 160A as an etching mask, the thick upper poly-Si film 150 is isotropically etched using a highly selective dry etching technique to form a poly-Si film pattern 150A. In this etching step, the thin native oxide film on the surface of the poly-Si film 120 serves as an etch stop.
Using the oxide film pattern 160A and poly-Si film pattern 150A as an implant mask, phosphorus ions are implanted into the semiconductor layer 100 to form n-type semiconductor regions 200A and 200B in the p-type semiconductor layer 100.
After the ion implant, as shown in FIG. 12C, silicon oxide films (sidewall spacers) 210A and 210B are selectively formed on the side surfaces of oxide film pattern 160A and poly-Si film pattern 150A using an anisotropic etching technique. The thin poly-Si film 120 is then selectively etched to form a wider poly-Si film pattern 120A (which acts as an overlapped gate) using the oxide films 210A and 210B as an etching mask.
Finally, as shown in FIG. 12D, using the silicon oxide films 210A and 210B and oxide film pattern 160A as an implant mask, arsenic ions with high doses are implanted into the semiconductor layer 100 to form n-type semiconductor regions 220A and 220B in the p-type semiconductor layer 100.
In the GOLD MOSFET, the n-type semiconductor region 200B at the end part (edge) of the drain is sufficiently overlapping (more than 0.2 .mu.m) the poly-Si pattern 120A. Due to this overlap (gate-drain overlap), the peak electric field at the drain end part is reduced as compared with that of other MOSFETs, for example, MOSFETs having a conventional LDD (lightly doped drain) structure. Thus, generation of hot carriers at the drain end part of the GOLD MOSFET is suppressed.
However, the conventional method of fabricating a GOLD MOSFET has the following disadvantages.
(1) Since a thin native oxide film is used as an etch stop in the step of etching the poly-Si film 150, it is necessary to use an etchant which has an etch selectivity (ratio of the etch rate of the poly-Si film relative to that of the native oxide film) of several hundreds, so as not to etch the thin native oxide film and poly-Si film 120. However, such an etchant having an etch selectivity of several hundreds isotropically etches the side surfaces of the poly-Si film pattern 150A, as shown in FIG. 12B. Therefore, the width of the upper poly-Si film pattern 150A is decreased from the width of the oxide film pattern 160A, and the resistance of the gate line is increased.
(2) Due to the side-etch of the poly-Si film pattern 150A as shown in FIG. 12B, the oxide film pattern 160A overhangs. This overhanging deteriorates the features (shapes) of the oxide films 210A and 210B left on the side surfaces of the poly-Si pattern 150A. Since these oxide film (sidewall spacers) 210A and 210B are used as an etching mask for etching the poly-Si film 120, variations in the features of the oxide film 210A and 210B lead to variations in the width of the poly-Si film 120A (gate length of the MOSFET).
(3) Presence of the native oxide film (0.5 to 1.0 nm thick) between the upper poly-Si film 150 and lower poly-Si film 120A results in a high electrical resistance of contacts between the poly-Si film pattern 150A and the poly-Si film pattern 120A.